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1. ⇒  (MHT CET 2023 13th May Morning Shift )

If two inputs of a NAND gate are shorted, the resulting gate is

A. an OR gate

B. an AND gate

C. a NOT gate

D. a NOR gate

Correct Option is (C)

When the two inputs of a NAND gate are shorted, the resulting gate behaves as a NOT gate. This is because a NAND gate outputs the opposite of the AND operation. When both inputs are the same (due to shorting), the NAND gate essentially inverts that single input signal.

To illustrate :

  • If the input is 0 (0 AND 0), a regular AND gate would output 0, but a NAND gate outputs the opposite, which is 1.

  • If the input is 1 (1 AND 1), a regular AND gate would output 1, but a NAND gate outputs the opposite, which is 0.

So, with both inputs shorted, the NAND gate effectively becomes a NOT gate, inverting whatever single input it receives.

Therefore, the correct answer is :

Option C : a NOT gate.

2. ⇒  (MHT CET 2023 12th May Evening Shift )

In the following digital logic circuit, the output Y will be '1' for inputs

MHT CET 2023 12th May Evening Shift Physics - Semiconductor Devices and Logic Gates Question 9 English

A. A = 0, B = 0

B. A = 0, B = 1

C. A = 1, B = 0

D. A = 1, B = 1

Correct Option is (D)

There are two NOR gates, one NOT gate, and one NAND gate.

Output of NAND gate: A B

Output of NOT and NOR Gate: A ¯ + B

Final output: ( A B ) + ( A + B )

So, the output Y is 1 only if the input A and B is 1.

A = 1 B = 1 Y = 1 1 + 1 + 1 Y = 1

3. ⇒  (MHT CET 2023 12th May Morning Shift )

The following logic gate combination is equivalent to

MHT CET 2023 12th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 8 English

A. NAND gate

B. OR gate

C. XOR gate

D. NOT gate

Correct Option is (C)

MHT CET 2023 12th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 8 English Explanation

Y = A B ( A + B ) Y = ( A + B ) ( A + B ) ( A B = A + B ) Y = A B + B A Y = A B + B A

This represents XOR gate.

4. ⇒  (MHT CET 2023 12th May Morning Shift )

The logic gate combination circuit shown in the figure performs the logic function of

MHT CET 2023 12th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 7 English

A. AND gate

B. NAND gate

C. OR gate

D. XOR gate

Correct Option is (A)

[Note: The gate at the output in the circuit is AND gate. It requires minimum two inputs. As, there is only one input the gate is not operational.]

5. ⇒  (MHT CET 2023 11th May Evening Shift )

In the digital circuit the inputs are as shown in figure. The Boolean expression for output Y is

MHT CET 2023 11th May Evening Shift Physics - Semiconductor Devices and Logic Gates Question 10 English

A. A + B + C

B. A B C

C. A B + C

D. A + B C

Correct Option is (C)

In the given circuit, there is AND, NOR and a NOT gate.

Output of AND gate: A B

Output of NOT gate: C

The boolean expression will be:

A B + C