6. ⇒ (MHT CET 2023 11th May Morning Shift )

In the case of NAND gate, if A and B are the inputs and $Y$ is the output then

A. $Y = A \cdot B$

B. $Y = \overset{―}{A - B}$

C. $Y = \overset{―}{A + B}$

D. $Y = \overset{―}{A \cdot B}$

Correct Option is (D)

Currently no explanation available

7. ⇒ (MHT CET 2023 10th May Evening Shift )

The output of an 'OR' gate is connected to both the inputs of a 'NAND' gate. The combination will serve as

A. OR gate

B. NOT gate

C. NOR gate

D. AND gate

Correct Option is (C)

MHT CET 2023 10th May Evening Shift Physics - Semiconductor Devices and Logic Gates Question 19 English Explanation

Output of OR gate	Output of NAND gate
0	1
1	0
1	0
1	0

Truth table of a NOR gate

A	B	Y
0	0	1
0	1	0
1	0	0
1	1	0

The output matches with that of a NOR gate.

$∴$ The combination represents a NOR gate.

8. ⇒ (MHT CET 2023 10th May Morning Shift )

To obtain the truth-table shown, from the following logic circuit, the gate G should be

MHT CET 2023 10th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 14 English

A. AND

B. NAND

C. OR

D. NOR

Correct Option is (D)

MHT CET 2023 10th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 14 English Explanation

The truth table for given configuration is as shown below,

Case	$A$	$B$	$C$	$A + C = Y$
$I$	0	0	$C_{1}$	$0 + C_{1} = 1$
$II$	0	1	$C_{2}$	$0 + C_{2} = 0$
$III$	1	0	$C_{3}$	$1 + C_{3} = 1$
$IV$	1	1	$C_{4}$	$1 + C_{4} = 1$

Considering case (I), in order to have output (Y) as $1, C_{1}$ has to be 1. For input values, $A = 0$ and $B = 0$ , if $C_{1}$ is to be high, the gate $G$ could be either NAND or NOR.

Considering case (II), in order to have output (Y) as $0, C_{2}$ has to be 0. For input values, $A = 0$ and $B = 1$ . If $C_{2}$ is to be 0 , the gate must be NOR.

9. ⇒ (MHT CET 2023 9th May Morning Shift )

To get the truth table shown, from the following logic circuit, the Gate G should be

MHT CET 2023 9th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 28 English

A. OR

B. AND

C. NOR

D. NAND

Correct Option is (B)

MHT CET 2023 9th May Morning Shift Physics - Semiconductor Devices and Logic Gates Question 28 English Explanation

Truth table for Y, with the possible values of C is,

A	C	Y
0	0	0
0	0	0
1	0, 1	1
1	0, 1	1

For gate G

	A	B	C
$(I)$	0	0	0
$(II)$	0	1	0
$(III)$	1	0	0, 1
$(IV)$	1	1	0, 1

$G$ is not a NOT gate as NOT gate takes only one input. (II) indicates $G$ is not a OR gate as OR gate would give high output for the inputs in (II). Also, (II) indicates it is not a XOR gate as XOR would also give high output for inputs in (II). Hence, the given truth table is satisfied only by AND gate.

10. ⇒ (MHT CET 2021 21th September Evening Shift )

Combination of NAND gates is shown in the figure. It is equivalent to

MHT CET 2021 21th September Evening Shift Physics - Semiconductor Devices and Logic Gates Question 31 English

A. AND gate

B. NOR gate

C. OR gate

D. X-OR gate

Correct Option is (C)

The two NAND gates whose two inputs are joined together behave like NOT gates. The truth table can be written as

A	B	y $_{1}$	y $_{2}$	y
0	0	1	1	0
0	1	1	0	1
1	0	0	1	1
1	1	0	0	1

We see that the output y is '1' if A or B or both are '1'. Hence it behaves as OR gate.

⇒Semiconductor Devices